Senior PD Engineer: Synthesis & STA

This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.

Key Responsibilities
* Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.
* Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.
* RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.
* Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.
* Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.
* Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.

Required Skills & Qualifications
* Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
* EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.
* Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
* RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
* Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
* Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
* Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.

Preferred Qualifications
* Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.
* Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
* Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.