CPU Core Design Verification Manager

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will lead our Bangalore-based CPU Core Design Verification team, driving both the technical strategy and the people leadership behind verification of our high-performance, out-of-order RISC-V CPUs. You will manage a team of core-level verification engineers, partner closely with our Santa Clara and Austin sites, and own delivery of core verification from architecture definition through tapeout readiness.

This role is hybrid based out of Bangalore, India, with regular collaboration across our globally distributed CPU organization.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

* 15+ years of CPU/DV experience, including 7+ years leading verification teams, with strong hands-on expertise in high-performance, out-of-order CPU verification.
* Deep microarchitecture & verification expertise, including ISA, RTL, UVM/CVM, testbench development, regressions, coverage, and complex debug.
* Strong people and technical leadership, with experience hiring, mentoring, developing engineers, and setting verification strategy and methodology across teams.
* Highly collaborative and execution-focused, comfortable working across time zones and driving cross-functional debug with Design, DV, Emulation, and Post-Silicon teams, including P0 issues and AI-assisted verification workflows.

What We Need

* Build and lead the Bangalore CPU Core DV team, owning hiring, mentoring, performance management, and team growth.
* Own verification strategy and execution for high-performance, out-of-order RISC-V CPU cores, covering ISA, microarchitecture, UVM/CVM methodology, infrastructure, and coverage.
* Drive cross-site execution with DV and design leads in Santa Clara and Austin, aligning coverage, schedules, tapeout readiness, and closure of critical bugs and coverage gaps.
* Stay technically engaged while leading the team, contributing to debug, code/testplan and architecture reviews, and championing AI-assisted tools for triage, stimulus generation, and coverage analysis.

What You Will Learn

* How Tenstorrent designs and verifies high-performance RISC-V CPU cores and clusters across a globally distributed organization.
* How to scale a verification team and its infrastructure across core, cluster, and chip-level environments spanning multiple sites.
* Techniques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus and methodology.
* How Tenstorrent applies AI across the DV lifecycle — from test planning and stimulus through regression debug, triage, and coverage analysis — using workflows designed to keep context tight and outputs auditable.
* How to build and run a high-performing verification organization inside a fast-growing, technically ambitious silicon company.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.